The present invention relates to a manufacturing method for a semiconductor device used, for example, for implanting impurity ions into a semiconductor substrate and activation annealing, and a semiconductor device.
In recent years, with a growing requirement for high-performance semiconductor devices, an approach of applying a stress to a channel region has been employed in order to increase drain current of a transistor.
The method of applying a stress may include a method of forming a film with a high stress, after formation of a gate electrode, and applying a stress to a channel region. The method may also include, for example, a method of etching a source/drain region in a Si-MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and epitaxially growing, in the region, a mixed crystal layer having a lattice constant different from that of a Si substrate.
In the latter method, as the mixed crystal layer, a SiGe layer is formed in order to apply a compressive stress to the channel region in the transverse direction in the case of a p-channel MOSFET (hereinafter, referred to as a “p-MOSFET”). A Si:C layer is formed in order to apply a tensile stress to the channel region in the transverse direction in the case of an n-channel MOSFET (hereinafter, referred to as an “n-MOSFET”). In both cases, as the contained Ge or C is higher, the mixed crystal layer is closer to the channel region, and the volume of the mixed crystal layer is larger (thicker film), the stress application to a channel layer is more effective as described, for example, in Japanese Patent Application Laid-Open No. 2007-36205 (claim 1, paragraph [0041] and so on).
However, if a mixed crystal layer containing Ge or C in a high concentration grows to a thickness greater than a critical film thickness, a crystal defect occurs to relax the stress. There is therefore a problem that it is difficult to secure a sufficient process margin for applying a high stress to a channel region while suppressing crystal defects.
On the other hand, improvement in performance of a semiconductor device by miniaturization of elements is studied. Since influences of parasitic resistance and short channel effects of MOSFETs constituting a semiconductor device increase with the miniaturization, it is required that an impurity diffusion layer be formed to have low resistance and to be shallow (shallow junction formation).
Heat treatment for impurity activation needs to be performed at a high temperature in order to reduce the resistance of an impurity diffusion layer. However, a conventional RTA (Rapid Thermal Anneal) diffuses impurities. It is therefore difficult to achieve both resistance reduction and shallow junction formation. To address this difficulty, an annealing method using a flash lamp or a laser capable of instantaneously supplying thermal energy is studied as described in Japanese Patent Application Laid-Open No. 2004-63574 (paragraph [0006] and so on).
However, a problem with this method is that instantaneous heating of the surface of a semiconductor substrate having semiconductor elements formed thereon increases the thermal stress inside the semiconductor substrate, causing dislocation and crystal defects to easily occur.